(1) Field of the Invention
The invention relates to a peripheral interface in the form of a computer connector for a system bus of a control computer, a peripheral connector for a peripheral device and a control unit serving for one-way transmission of a predetermined amount of data from the control computer to the peripheral device and/or vice versa. The control unit accesses via the system bus a working memory range of the control computer preassigned to it. The working memory range acts as a buffer. The present invention also concerns a process for transmitting data from a control computer to a peripheral device and/or vice versa.
(2) Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 1.98
A peripheral interface provides communication between a control computer and one or more peripheral devices by electronic data transfer. Conventionally, peripheral devices are connected via standard interfaces such as USB (universal serial bus), Ethernet or Firewire, which provide a separate bus on the peripheral side. The data transmission of the peripheral interface is essentially controlled by the control computer, more precisely by its central processing unit, CPU. This is usually accomplished by driver software [a computer program] executed by the CPU, which triggers the ability of the interface device to access working memory (random access memory (RAM)), and the control computer. Access to the RAM is accomplished cyclically by direct memory access, DMA, via the system bus of the control computer. The peripheral interface has a DMA controller for this purpose. Typically, the DMA controller transmits a data block in each DMA cycle. The size of the data block generally corresponds to a single memory page of the RAM. In the case of a large quantity of data, accordingly, a large number of data blocks must be transferred. Therefore, a corresponding number of DMA cycles is required.
The driver software reports each DMA cycle to the DMA controller of the peripheral device. The control computer then executes other software, e.g. an application program with user interaction. Later, the control computer receives confirmation of the complete transfer in the form of an interrupt request, IRQ. In response to the interrupt request, the regular program execution is interrupted and in its place the driver program executes. The driver program continues the data transmission by initiating the next DMA cycle. To achieve a high constant data transmission speed, the driver software must react quickly upon such an interrupt request in order to initiate the next DMA cycle at the right time. Especially in a real-time critical system, a maximal reaction time may not be exceeded in order to prevent gaps in the data transfer. However, if the control computer uses a non-real-time-enabled operating system, a deterministic treatment of an interrupt request for a DMA cycle is not possible. The reaction time for an interrupt request may increase almost arbitrarily here if the workload of the system increases or if there are a large number of simultaneous DMA transfer processes. The number of simultaneous DMA transfer processes increases with the desired data transmission speed and is also determined by the magnitude of the data quantity to be transmitted.
There are known DMA controllers to which several memory access steps can be assigned for a single DMA cycle in order to reduce the number of DMA cycles required. The DMA controller of the peripheral interface carries out these steps independently and in turn communicates their completion to the driver software by an interrupt request. For this purpose, the control computer, for example, upon initiation of a DMA cycle, transmits a list of data blocks to be transferred to the DMA controller. This process is called “scatter gathering” or “chained DMA.”
A common feature of the processes and arrangements mentioned above is the fact that the software of the control computer must specify detailed processing steps for the DMA controller of the peripheral interface and communicate them to the hardware in a timely manner before the still running data transmission ends so that the data stream is not interrupted. The response time of a peripheral device to instructions sent by the control computer and the response time of the control computer to a transmitted change in a state of the peripheral device are therefore determined in particular by the data transmission rate of the respective peripheral interfaces, which, in turn, depend, inter alia, on how often the control computer must intervene in the course of the data transmission.
The unburdening of the CPU of the control computer by special input/output processors, e.g., type 8089, for conducting data transfer processes, is conventionally used. For this purpose, the controller tasks of the data transfer can be accepted in part by such an I/O processor instead of the software program executed by the CPU. I/O processors can be programmed for independent transfer of data between individual links of the system bus without assistance from the main processor. However, their use is expensive and requires a relatively large amount of installation space. Their programming is also costly and inflexible. An I/O processor also generates an interrupt request to the CPU of the control computer at the end of a transmission, which must react in a time-critical manner so that the data flow is not terminated. Therefore, for time-critical data transfers, a real-time enabled operating system must nevertheless be used.
In the known processes for control and data recording by laser scanning microscopes (LSM), the data segments to be transferred are typically in the form of an uninterrupted data stream. Transfer of the data segments must be initiated anew each time and amounts to only about 10 kilobytes in each case. The size of these data segments is determined essentially by the size of the memory of the necessary buffering devices of the control computer and peripheral interface. These buffer devices with a fast, static memory are available only in a limited memory size and are very expensive. In such cases, the longest reaction times to interrupt requests of fewer than 200 μs are required in which, if necessary, new data must be computed and delivered later. The conventional peripheral interfaces used in LSM systems therefore impose high operating costs on the control computer in the form of short reaction times of the driver software coupled with frequent interrupt requests. If the driver software, i.e. the control computer, reacts too slowly, there is no consistent stream of control data and/or the incoming data is lost. In the case of interruption of the control data stream, components of the LSM, e.g., the scanner mirrors, may be damaged, which must be avoided. These critical requirements on an LSM system were previously fulfilled only with the aid of a real-time operating system. In the case of a non-real-time enabled operating system, a much lower data transfer speed had to be used. As a consequence, scanning processes on a sample must be performed only at a low speed or only a small number of detection channels can be used.
Thus, the present invention has the objective of improving a peripheral interface of the type mentioned initially in such a way that, especially in the case of a non-real-time-enabled operating system of the control computer, operating costs are reduced and data can be transferred at a high transfer rate without gaps and without losses between the control computer and the peripheral device. In particular, the intention is to permit the fast transfer of large volumes of data in LSM systems.